Physical Design

We Design Physical IC for You

Physical Design Competency

Asmicore offers high-efficiency DFT solutions for complex SoCs and advanced nodes. We streamline testing and debugging to accelerate time-to-market while meeting PPA goals. Our end-to-end DFT services include scan insertion, ATPG, MBIST, Logic BIST, and more. We ensure RTL and physical-level integration, supporting power-gated and ECO-heavy designs. Our flows are compatible with Synopsys, Cadence, and Siemens EDA tools. Whether you’re developing automotive chips, mobile SoCs, AI accelerators, or low-power IoT devices, we deliver effective cross-domain DFT solutions. With Asmicore, you gain agility, reliability, and innovation in every stage of your DFT journey and we ensure with care that Clients benefit from full-chip or block-level DFT ownership based on specific design needs.

“Everything is designed to turn insights into action – faster decisions, cleaner execution, and better results.”

— Founder & CEO

Summary on Competency

Flow Development & Design Planning

  • Flow development and automation
  • Hierarchical, full-chip, block-level flow
  • Bump planning and analysis
  • RDL routing from bump to different I/O pads (signal, power)
  • Different vendors’ IP integration
  • Constraint file development across different modes
  • MMMC creation and validation
  • Logical and physical-aware synthesis
  • Floorplanning and power planning

Placement, Optimization & Clocking

  • PPA (Power, Performance, Area) scaling
  • DFT (scan insertion) flow
  • Custom placement and routing
  • Placement and optimization
  • Scan chain reordering
  • Clock Tree Synthesis (CTS)
  • Different clocking structures: fishbone, H-tree, clock mesh
  • Routing and optimization

Signoff & Physical Verification

  • Logic Equivalence Check (LEC)
  • Merge GDS generation
  • Physical Verification (DRC, ERC, LVS, Antenna, DFM)
  • Parasitic extraction
  • DRV and timing signoff closure
  • Power signoff closure (IR, EM)

ECO & Tapeout Closure

  • Timing ECO implementation for different modes
  • Final timing closure
  • Final power closure
  • Final physical verification closure
  • GDSII/tapeout readiness