Physical Design
We Design Physical IC for You
Physical Design Competency
At Asmicore Semiconductor, we transform complex ideas into silicon reality through our complete physical design solutions, spanning from RTL to GDSII. Whether it’s a high-performance IP block or a full-chip SoC, we bring precision, innovation, and engineering excellence to every project. Our team thrives on tackling the most demanding challenges in power, performance, and area optimization. With a sharp focus on quality and first-time-right execution, we partner with our clients to drive successful tapeouts and accelerate time-to-market for the next generation of semiconductor products.
“Everything is designed to turn insights into action – faster decisions, cleaner execution, and better results.”
— Founder & CEO
Summary on Competency
Flow Development & Design Planning
- Flow development and automation
- Hierarchical, full-chip, block-level flow
- Bump planning and analysis
- RDL routing from bump to different I/O pads (signal, power)
- Different vendors’ IP integration
- Constraint file development across different modes
- MMMC creation and validation
- Logical and physical-aware synthesis
- Floorplanning and power planning
Placement, Optimization & Clocking
- PPA (Power, Performance, Area) scaling
- DFT (scan insertion) flow
- Custom placement and routing
- Placement and optimization
- Scan chain reordering
- Clock Tree Synthesis (CTS)
- Different clocking structures: fishbone, H-tree, clock mesh
- Routing and optimization
Signoff & Physical Verification
- Logic Equivalence Check (LEC)
- Merge GDS generation
- Physical Verification (DRC, ERC, LVS, Antenna, DFM)
- Parasitic extraction
- DRV and timing signoff closure
- Power signoff closure (IR, EM)
ECO & Tapeout Closure
- Timing ECO implementation for different modes
- Final timing closure
- Final power closure
- Final physical verification closure
- GDSII/tapeout readiness