Analog & Mixed-Signal Design
Where Precision Meets Performance
Analog & Mixed-Signal Design
At Asmicore Semiconductor, we provide comprehensive Analog & Mixed-Signal Design services, enabling the development of high-performance, low-power, and reliable custom ICs for advanced semiconductor applications. Our engineering expertise spans from analog circuit implementation and full-custom layout to mixed-signal IP integration and signoff verification. We focus on delivering robust, manufacturable designs that meet stringent performance, matching, noise, and reliability requirements across a wide range of process technologies. Whether supporting standalone analog IPs or full-chip mixed-signal SoCs, our team works closely with clients to accelerate development while ensuring first-pass silicon success.
“Everything is designed to turn insights into action – faster decisions, cleaner execution, and better results.”
— Founder & CEO
Summary on Competency
Custom Analog Layout & Matching
- Full-custom analog layout for block-level and mixed-signal IPs
- Device placement, floorplanning and hierarchical layout implementation
- Matching-critical layout techniques:
- Common-Centroid
- Interdigitated
- Symmetrical Layout
- Guard rings, shielding and substrate isolation
- Noise-aware layout techniques
- Layout optimization for matching, parasitic reduction and manufacturability
- Custom passive component layout — resistors, capacitors, MOM/MIM capacitors
- Power distribution planning and analog signal routing
Verification & Signoff
- DRC, LVS and ERC closure
- Parasitic Extraction (PEX)
- EM/IR analysis
- Analog verification and signoff
- Reliability verification
- Post-layout verification and optimization
- Signoff support for analog and mixed-signal IPs
- Cadence: Virtuoso, Virtuoso Layout XL, Pegasus
- Synopsys: Custom Compiler, PrimeSim, PrimeSim EMIR
- Siemens: Calibre
- Other: IC Validator (ICV) and industry-standard custom design and verification flows
Analog & Mixed-Signal IP Design
- LDOs
- Bandgap References
- Current Mirrors
- Comparators
- Operational Amplifiers
- Charge Pumps
- Oscillators
- Custom analog and mixed-signal IP blocks
- ADCs and DACs
- PLLs and DLLs
- Clock Generation circuits
Reliability, Integration & Design Optimization
- Electromigration (EM) and reliability-aware layout implementation
- ESD-aware layout practices
- Latch-up prevention
- Analog IP integration into subsystem and SoC-level designs
- Layout reviews and design optimization
- Power integrity and reliability considerations
- Mixed-signal IP integration and interface considerations