Physical Design Competency
At Asmicore Semiconductor, we transform complex ideas into silicon reality through our complete physical design solutions, spanning from RTL to GDSII. Whether it's a high-performance IP block or a full-chip SoC, we bring precision, innovation, and engineering excellence to every project. Our team thrives on tackling the most demanding challenges in power, performance, and area optimization. With a sharp focus on quality and first-time-right execution, we partner with our clients to drive successful tapeouts and accelerate time-to-market for the next generation of semiconductor products.
Summary on Competency
- Flow development and automation
- Hierarchical, full chip, block level flow
- Bump planning and analysis
- RDL routing from Bump to different IO pads (signal, power)
- Different vendors IP integration
- Constraint file development on different modes
- MMMC creation and validation
- Logical and physical aware synthesis
- PPA (Power, Performance, Area) Scaling
- DFT (scan insertion) flow
- Floorplanning and Power planning
- Custom placement and routing
- Placement and optimization, scan chain reordering
- Clock Tree Synthesis (CTS)
- Different clocking structures: fishbone, H-tree, clock mesh
- Routing and Optimization
- Logic Equivalence Check (LEC)
- Merge GDS generation
- Physical Verification (DRC, ERC, LVS, Antenna, DFM)
- Parasitic Extraction
- DRV and Timing Signoff Closure
- Power Signoff Closure (IR, EM)
- Timing ECO implementation for different modes