Design For Test (DFT)
The DFT team is dedicated to achieving testability to detect manufacturing defects in the designs. As DFT is a vital and often challenging step, our team simplifies and optimizes it, ultimately reducing costs and accelerating time-to-market. With expertise in scan insertion, Automatic Test Pattern Generation (ATPG), Boundary Scan/JTAG, and coverage analysis, we provide comprehensive DFT solutions at both the IP and SoC levels. Our team focuses on maximizing test coverage, reducing test time, and improving yield, ensuring that your final product meets the highest quality standards.
Capabilities Summary
- Development of DFT Architecture & Specification
- Scan Insertion with or without Compression
- Insertion of DFT features like Test Point, Wrapper, etc. for coverage improvement
- Coverage analysis and improvement
- LINT and LEC on DFT inserted design
- Low-power ATPG and low-power compression
- DFT Scannability check with Spyglass
- Test vector generation using ATPG
- Gate-level simulation and debugging with no-timing and timing